1. Field of the Invention
The present invention relates to a magnetic memory device, and more specifically, it relates to a magnetic memory device including a storage element exhibiting a ferromagnetic tunnel effect.
2. Description of the Prior Art
An MRAM (magnetic random access memory) is generally known as a nonvolatile memory magnetically recording data. This MRAM is disclosed in detail in Nikkei Electronics, 1999, 11.15 (No. 757), pp, 49 to 56 etc.
FIGS. 18 and 19 are schematic diagrams for illustrating the structure of a storage element 110 of the MRAM disclosed in the aforementioned literature. Referring to FIG. 18, the storage element 110 of the conventional MRAM comprises a ferromagnetic layer 101, another ferromagnetic layer 103 and a nonmagnetic layer 102 arranged between the ferromagnetic layers 101 and 103.
The ferromagnetic layer 101 is harder to invert than the ferromagnetic layer 103. A substance exhibiting ferromagnetism, which is magnetism provided by magnetic atoms or free atoms of a metal arranging magnetic moments in parallel with each other by positive exchange interaction for forming spontaneous magnetization, is referred to as a ferromagnetic substance. The ferromagnetic layers 101 and 103 consist of such a ferromagnetic substance. In general, a GMR (giant magnetoresistance) film employing a metal is applied to the nonmagnetic layer 102. Recently, a TMR (tunneling magnetoresistance) film employing an insulator is developed for the nonmagnetic layer 102. The TMR film advantageously has larger resistance than the GMR film. More specifically, the MR ratio (rate of resistance change) of the GMR film is at the level of 10%, while that of the TMR film is at least 20%. The storage element 110 consisting of the TMR film is hereinafter referred to as a TMR element 110.
The principle of storage of the conventional MRAM employing the TMR element 110 is now described with reference to FIGS. 18 and 19. Such a state that the two ferromagnetic layers 101 and 103 are magnetized in the same direction (parallel) is associated with data xe2x80x9c0xe2x80x9d, as shown in FIG. 18. Such a state that the two ferromagnetic layers 101 and 103 are magnetized in opposite directions (antiparallel) is associated with data xe2x80x9c1xe2x80x9d, as shown in FIG. 19. The TMR element 110 exhibits small resistance (R0) when magnetized in the parallel direction, while exhibiting large resistance (R1) when magnetized in the antiparallel directions. The data xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d are distinguished from each other through this property of the TMR element 110 having the resistance varying with the directions of magnetization.
FIG. 20 is a block diagram showing the overall structure of a conventional MRAM 150 having memory cells each formed by a single TMR element and a single transistor. The structure of the conventional MRAM 150 is now described with reference to FIG. 20.
A memory cell array 151 is formed by a plurality of memory cells 120 arranged in the form of a matrix (FIG. 20 shows only four memory cells 120 for simplifying the illustration). Each memory cell 120 is formed by a TMR element 110 and an NMOS transistor 111.
In the memory cells 120 arranged in a row direction, gates of the NMOS transistors 111 are connected to common read word lines RWL1 to RWLn. In the memory cells 120 arranged in the row direction, further, rewrite word lines WWL1 to WWLn are arranged on first ferromagnetic layers of the TMR elements 110.
In the memory cells 120 arranged in a column direction, first ferromagnetic layers of the TMR elements 110 are connected to common bit lines BL1 to BLn.
The read word lines RWL1 to RWLn are connected to a row decoder 152, and the bit lines BL1, to BLn are connected to a column decoder 153.
Externally specified row and column addresses are input in an address pin 154. The row and column addresses are transferred from the address pin 154 to an address latch 155. In the addresses latched by the address latch 155, the row address is transferred to the row decoder 152 through an address buffer 156, while the column address is transferred to the column decoder 153 through the address buffer 156.
The row decoder 152 selects a read word line RWL corresponding to the row address latched by the address latch 155 from the read word lines RWL1 to RWLn while selecting a rewrite word line WWL corresponding to the row address latched by the address latch 155 from the rewrite word lines WWL1 to WWLn. Further, the row decoder 152 controls the potentials of the read word lines RWL1 to RWLn and the rewrite word lines WWL1 to WWLn on the basis of a signal from a voltage control circuit 157.
The column decoder 153 selects a bit line BL corresponding to the column address latched by the address latch 155 from the bit lines BL1 to BLn, while controlling the potentials of the bit lines BL1 to BLn on the basis of a signal from another voltage control circuit 158.
Externally specified data is input in a data pin 159. This data is transferred from the data pin 159 to the column decoder 153 through an input buffer 160. The column decoder 153 controls the potentials of the bit lines BL1 to BLn in correspondence to the data.
Data read from an arbitrary memory cell 120 is transferred from the bit lines BL1 to BLn to a sense amplifier group 161 through the column decoder 153. The sense amplifier group 161 is formed by current sense amplifiers. The data determined by the sense amplifier group 161 is output from an output buffer 162 through the data pin 159.
A control core circuit 163 controls the operations of the aforementioned circuits 152 to 162.
A write (rewrite) operation and a read operation of the conventional MRAM 150 having the aforementioned structure are now described.
(Write Operation)
In the write operation, orthogonal currents are fed to the selected rewrite word line WWL and the selected bit line BL. Thus, only the TMR element 110 arranged on the intersection between the bit line BL and the rewrite word line WWL can be rewritten. More specifically, the currents flowing to the rewrite word line WWL and the bit line BL generate magnetic fields, so that the sum (composite field) of the two magnetic fields acts on the TMR element 110. The direction of magnetization of the TMR element 110 is inverted from xe2x80x9c1xe2x80x9d to xe2x80x9c0xe2x80x9d, for example, due to the composite field.
The remaining TMR elements 110 include those fed with no currents and those only unidirectionally fed with currents. In the TMR elements 110 fed with no currents, no magnetic fields are generated and hence the directions of magnetization remain unchanged. In the TMR elements 110 only unidirectionally fed with currents, the magnitudes of generated magnetic fields are insufficient for inverting the directions of magnetization. Therefore, the directions of magnetization remain unchanged also in the TMR elements 110 only unidirectionally fed with currents.
As hereinabove described, the direction of magnetization of the TMR element 110 located on the intersection between the bit line BL and the rewrite word lines WWL corresponding to the selected address can be changed to that shown in FIG. 18 or 19 by feeding currents to the selected bit line BL and the selected rewrite word line WWL. Thus, the data xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d can be written.
Read Operation
In order to read the data written in the aforementioned manner, a voltage is applied to the read word line RWL for rendering the NMOS transistor 111 conductive. In this state, a determination is made as to whether or not the value of a current flowing to the bit line BL is larger than a reference current value, thereby determining xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d.
In this case, the data xe2x80x9c0xe2x80x9d shown in FIG. 18 exhibits a small resistance value (R0) due to the parallel direction of magnetization. Therefore, the value of the current flowing to the bit line BL is larger than the reference current value. On the other hand, the data xe2x80x9c1xe2x80x9d shown in FIG. 19 exhibits a larger resistance value (R1) than that shown in FIG. 18 due to the antiparallel directions of magnetization. Therefore, the value of the current flowing to the bit line BL is smaller than the reference current value.
In the aforementioned conventional MRAM 150, the potential of the bit line BL must be set to a slight level (not more than 0.4 V) for detecting the current value in data reading. This is because resistance change in the TMR element 110 cannot be confirmed unless potential difference applied across the TMR element 110 is slight. Therefore, the potential difference applied across the TMR element 110 must be slight (not more than 0.4 V), leading to the value of a small current. In general, the structure of a sense amplifier (amplifier) is disadvantageously complicated for detecting such the value of a small current. Further, the reading speed is disadvantageously reduced for detecting the small current value.
An object of the present invention is to provide a magnetic memory device not complicating the structure of a sense amplifier (amplifier).
Another object of the present invention is to provide a magnetic memory device capable of improving a reading speed as compared with a case of determining data by detecting the value of a small current.
Still another object of the present invention is to simplify replacement from a DRAM in the aforementioned magnetic memory device.
A magnetic memory device according to a first aspect of the present invention comprises a memory cell consisting of a first storage element and a second storage element exhibiting a ferromagnetic tunnel effect and first and second transistors connected to the first and second storage elements respectively, a word line connected to control terminals of the first and second transistors, a bit line connected to the first storage element through the first transistor, an inverted bit line connected to the second storage element through the second transistor for forming a pair of bit lines with the bit line, and an amplifier connected to the bit line and the inverted bit line. The magnetic memory device inputs a signal in a selected word line while reading potential difference caused between the bit line and the inverted bit line by inputting the signal in the word line through the amplifier in data reading.
In the magnetic memory device according to the first aspect, the memory cell is formed by the pair of first and second storage elements exhibiting a ferromagnetic tunnel effect and the pair of first and second transistors while the amplifier detects the potential difference between the bit line and the inverted bit line connected to the pair of first and second storage elements, whereby data can be readily read. Thus, it is not necessary to detect the value of a small current flowing to the bit line dissimilarly to the case of a conventional memory cell formed by a storage element exhibiting a ferromagnetic tunnel effect and a transistor. Consequently, the structure of the amplifier is not complicated. Further, the potential difference caused between the bit line and the inverted bit line by inputting the signal in the word line is read through the amplifier, whereby detection can be readily made also when the storage elements have high resistance, dissimilarly to the conventional case of reading the value of a small current flowing to the bit line.
In the magnetic memory device according to the first aspect, the amplifier detects the potential difference between the bit line and the inverted bit line as described above, whereby data stored in the magnetic memory device can be read through a simple amplifier similar to an amplifier (sense amplifier) employed for a conventional DRAM. Thus, no sense amplifier having a complicated structure may be employed dissimilarly to the case of the conventional memory cell formed by a storage element exhibiting a ferromagnetic tunnel effect and a transistor, whereby high-speed reading is enabled. Further, the structure of the sense amplifier, the circuit structure and an operating method are similar to those of the conventional DRAM, whereby the technique of the DRAM can be utilized as such. Consequently, replacement from the DRAM can be readily attained.
In the magnetic memory device according to the aforementioned first aspect, each of the first storage element and the second storage element preferably includes a first magnetic layer and a second magnetic layer, harder to invert than the first magnetic layer, opposed to the first magnetic layer through an isolation barrier layer, and the second magnetic layer of the first storage element and the second magnetic layer of the second storage element are preferably connected with each other, while the magnetic memory device preferably further comprises a sub-word line for lowering the potentials of the second magnetic layer of the first storage element and the second magnetic layer of the second storage element to a ground potential in response to a rise timing of the signal to the word line. According to this structure, the sub-word line can readily lower the potentials of the second magnetic layers of the first and second storage elements toward the ground potential. Thus, potential difference can be caused between the bit line and the inverted bit line due to the difference between the resistance values of the first and second storage elements when lowering the potentials of the second magnetic layers of the first and second storage elements to the ground potential. Stored data can be readily detected by detecting the potential difference through the amplifier.
In the magnetic memory device according to the aforementioned first aspect, a fall timing of the signal to the word line is preferably set before the potential of a second magnetic layer of the first storage element and the potential of a second magnetic layer of the second storage element reach a ground potential. According to this structure, disappearance of the potential difference between the bit line and the inverted bit line can be prevented. The potential difference between the bit line and the inverted bit line is caused only in a transient state. When the potentials of the second magnetic layers of the first and second storage elements reach the ground potential, therefore, the potentials of the bit line and the inverted bit line connected to the first magnetic layers also reach the ground potential. Consequently, the A potential difference between the bit line and the inverted bit line disappears. According to the present invention, the signal to the word line falls before the potentials of the second magnetic layers of the first and second storage elements reach the ground potential, so that the amplifier can detect the potential difference between the bit line and the inverted bit line before the potential difference disappears.
The magnetic memory device according to the aforementioned first aspect preferably further comprises an isolation transistor for isolating the amplifier from the bit line and the inverted bit line in response to a fall timing of the signal to the word line. According to this structure, the isolation transistor isolates the amplifier from the bit lie and the inverted bit line before the potentials of the second magnetic layers of the first and second storage elements reach the ground potential, whereby the amplifier can read the potential difference between the bit line and the inverted bit line.
In the magnetic memory device according to the aforementioned first aspect, the first storage element and the second storage element preferably store inverted data. According to this structure, the data can be readily read due to the difference in resistance between the first and second storage elements.
The magnetic memory device according to the aforementioned first aspect preferably further comprises a dummy bit line connected to the first storage element through the first transistor and a detection circuit detecting a fall timing of the dummy bit line. According to this structure, a fall timing of the bit line can be detected through the dummy bit line and the detection circuit. Thus, when the amplifier detects the potential difference between the bit line and the inverted bit line at the detected timing, the stored data can be readily read. In this case, the magnetic memory device preferably further comprises an isolation transistor for isolating the amplifier from the bit line and the inverted bit line in response to the fall timing of the dummy bit line detected by the detection circuit, and the aforementioned amplifier is preferably activated in response to the fall timing of the dummy bit line detected by the detection circuit. According to this structure, the amplifier can readily detect the potential difference between the bit line and the inverted bit line.
In the magnetic memory device according to the aforementioned first aspect, the detection circuit preferably includes a first transistor having a gate receiving an applied input voltage and a second transistor having a gate receiving an applied reference voltage, and a current flowing to the first transistor is preferably rendered larger than a current flowing to the second transistor thereby outputting a low level when the input voltage is equivalent to the reference voltage. According to this structure, the output can be effectively prevented from being undefined when the input voltage is identical to the reference voltage. In this case, the gate width of the first transistor may be larger than the-gate width of the second transistor, or the gate length of the first transistor may be smaller than the gate length of the second transistor.
In the magnetic memory device according to the aforementioned first aspect, a current is preferably fed to a selected sub-word line downward from above while feeding currents of opposite directions to the bit line and the inverted bit line in data writing, thereby writing inverted data in the first magnetic layer of the first storage element and the first magnetic layer of the second storage element. According to this structure, data can be readily written.
A magnetic memory device according to a second aspect of the present invention comprises a memory cell consisting of a storage element exhibiting a ferromagnetic tunnel effect including a first magnetic layer, a second magnetic layer having a surface opposed to a surface of the first magnetic layer through a first isolation barrier layer and a third magnetic layer opposed to another surface of the second magnetic layer through a second isolation barrier layer and first and second transistors connected to the first magnetic layer and the third magnetic layer of the storage element respectively, a word line connected to control terminals of the first and second transistors, a bit line connected to the first magnetic layer through the first transistor, an inverted bit line connected to the third magnetic layer through the second transistor for forming a pair of bit lines with the bit line, and an amplifier connected to the bit line and the inverted bit line. The magnetic memory device inputs a signal in a selected word line while reading potential difference caused between the bit line and the inverted bit line by inputting the signal in the word line in data writing.
In the magnetic memory device according to the second aspect, the memory cell is formed by the single storage element exhibiting a ferromagnetic tunnel effect including the first, second and third magnetic layers and the pair of first and second transistors while the amplifier detects the potential difference between the bit line and the inverted bit line connected to the first and third magnetic layers, whereby data can be readily read. Thus, it is not necessary to detect the value of a small current flowing to the bit line dissimilarly to the case of the conventional memory cell formed by a storage element exhibiting a ferromagnetic tunnel effect and a transistor. Consequently, the structure of the amplifier is not complicated. Further, the potential difference caused between the bit line and the inverted bit line by inputting the signal in the word line is read through the amplifier, whereby detection can be readily performed also when the storage element has high resistance, dissimilarly to the conventional case of reading the value of a small current flowing to the bit line.
In the magnetic memory device according to the second aspect, further, the memory cell is formed by the single storage element exhibiting a ferromagnetic tunnel effect including the first, second and third magnetic layers and the pair of first and second transistors, whereby the area of the memory cell can be reduced as compared with a memory cell formed by two storage elements and two transistors.
In the magnetic memory device according to the second aspect, in addition, the amplifier detects the potential difference between the bit line and the inverted bit line, whereby data stored in the magnetic memory device can be read through a simple amplifier similar to an amplifier (sense amplifier) applied to a conventional DRAM. Thus, no sense amplifier having a complicated structure may be employed dissimilarly to the case of the conventional memory cell formed by a storage element exhibiting a ferromagnetic tunnel effect and a transistor, whereby high-speed reading is enabled. The structure of the sense amplifier, the circuit structure and an operating method are similar to those of a conventional DRAM, whereby the technique of the DRAM can be utilized as such. Consequently, replacement from a DRAM can be readily attained.
In the magnetic memory device according to the aforementioned second aspect, the first magnetic layer preferably includes a sidewall-shaped first magnetic layer formed on a side surface of the second magnetic layer through the first isolation barrier layer, and the third magnetic layer preferably includes a sidewall-shaped third magnetic layer formed on another side surface of the second magnetic layer through the second isolation barrier layer. According to this structure, the single storage element consisting of the first, second and third magnetic layers can be readily formed. In this case, the sidewall shaped first and third magnetic layers are preferably formed by forming a magnetic material layer through an isolation barrier material layer to cover the second magnetic layer and thereafter anisotropically etching the magnetic material layer. According to this structure, the single storage element consisting of the first, second and third magnetic layers can be readily formed through a process similar to a conventional sidewall forming process.
In the magnetic memory device according to the aforementioned second aspect, the first magnetic layer and the third magnetic layer are preferably formed in a staggered manner with respect to the second magnetic layer.
In the magnetic memory device according to the aforementioned second aspect, the second magnetic layer of the storage element is preferably formed to be harder to invert than the first magnetic layer and the third magnetic layer, and the magnetic memory device preferably further comprises a sub-word line for lowering the potential of the second magnetic layer of the storage element to a ground potential in response to a rise timing of the signal to the word line. According to this structure, the sub-word line can readily lower the potential of the second magnetic layer of the storage element toward the ground potential. Thus, potential difference can be caused between the bit line and the inverted bit line due to difference in the resistance value of the storage element. The amplifier detects the potential difference, so that stored data can be readily detected.
In the magnetic memory device according to the aforementioned second aspect, a fall timing of the signal to the word line is preferably set before the potential of the second magnetic layer of the storage element reaches a ground potential. According to this structure, disappearance of the potential difference between the bit line and the inverted bit line can be prevented. The potential difference between the bit line and the inverted bit line is caused only in a transient state. When the potential of the second magnetic layer of the storage element reaches the ground potential, therefore, the potentials of the bit line and the inverted bit line connected to the first and third magnetic layers also reach the ground potential. Consequently, the potential difference between the bit line and the inverted bit line disappears. According to the present invention, the signal to the word line falls before the potential of the second magnetic layer of the storage element reaches the ground potential, whereby the amplifier can detect the potential difference between the bit line and the inverted bit line before the potential difference disappears.
The magnetic memory device according to the aforementioned second aspect preferably further comprises an isolation transistor for isolating the amplifier from the bit line and the inverted bit line in response to a fall timing of the signal to the word line. According to this structure, the isolation transistor isolates the amplifier from the bit line and the inverted bit line before the potential of the second magnetic layer of the storage element reaches the ground potential, whereby the amplifier can read the potential difference between the bit line and the inverted bit line.
In the magnetic memory device according to the aforementioned second aspect, the first magnetic layer and the third magnetic layer preferably store inverted data. According to this structure, data can be readily read through the difference in resistance between the first and second magnetic layers and the third and second magnetic layers.
A magnetic memory device according to a third aspect of the present invention comprises a memory cell consisting of a storage element exhibiting a ferromagnetic tunnel effect including a first magnetic layer, a second magnetic layer having a surface opposed to a surface of the first magnetic layer through a first isolation barrier layer and a third magnetic layer opposed to another surface of the second magnetic layer through a second isolation barrier layer, and first and second transistors connected to the first magnetic layer and the third magnetic layer of the storage element respectively.
In the magnetic memory device according to the third aspect, the memory cell is formed by the single storage element exhibiting a ferromagnetic tunnel effect including the first, second and third magnetic layers and the pair of first and second transistors as described above, whereby the area of the memory cell can be reduced as compared with a memory cell formed by two storage elements and two transistors.
In the magnetic memory device according to the aforementioned third aspect, the first magnetic layer preferably includes a sidewall-shaped first magnetic layer formed on a side surface of the second magnetic layer through the first isolation barrier layer, and the third magnetic layer preferably includes a sidewall-shaped third magnetic layer formed on another side surface of the second magnetic layer through the second isolation barrier layer. According to this structure, the single storage element consisting of the first, second and third magnetic layers can be readily formed. In this case, the sidewall-shaped first and third magnetic layers are preferably formed by forming a magnetic material layer through an isolation barrier material layer to cover the second magnetic layer and thereafter anisotropically etching the magnetic material layer. According to this structure, the single storage element consisting of the first, second and third magnetic layers can be readily formed through a process similar to a conventional sidewall forming process.
In the magnetic memory device according to the aforementioned third aspect, the first magnetic layer and the third magnetic layer are preferably formed in a staggered manner with respect to the second magnetic layer.
In the magnetic memory device according to the aforementioned third aspect, the first magnetic layer and the third magnetic layer preferably store inverted data. According to this structure, data can be readily read through difference in resistance between the first and second magnetic layers and the third and second magnetic layers.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.